The Layout of a PCell represents the physical implementation of your design. This means it’s made of a set of geometrical elements that belong to a certain layer. It’s also possible to add additional information like port and device labels.
All layout information of your PCell is captured in the
Typically the structure of a PCell with a LayoutView will look as follows:
import ipkiss3.all as i3 class MyCell(i3.PCell): class Layout(i3.LayoutView): # some layout specific properties length = i3.PositiveNumberProperty(default=10, doc="length") width = i3.PositiveNumberProperty(default=2, doc="some width") def _generate_instances(self, insts): # In _generate_instances, we'll specify the # references to child layouts def _generate_elements(self, elems): # in _generate_elements Geometrical Elements # are added def _generate_ports(self, ports): # Used to specify the input & output of your component
Separating the definition of all components of a LayoutView helps to assure that your LayoutView is well structured.
The Layouting capabilities in IPKISS are quite extensive, which is why the reference manual is split into a few themes:
- Elements & Layers
- Elements are the basic building blocks of the layout. These can be geometric data drawn on a certain layer, or references to other PCells for building hierarhhical layouts.
- Shapes & Geometry
- All layoutviews are in the end composed of a set of the geometrical primitives. Use this part of the reference to find out how to build the geometry of your layout.
- Ports are location on the layout where connections are made.
- Creates a path from one point to another, this path can then be used to create a waveguide or another type of trace.
- Importing from GDSII
- If you have existing GDSII layouts it is possible to import them into IPKISS.
- Installing IPKISS
- IPKISS Reference
- Picazzo Library Reference
- IPKISS.eda user manual